Two-Dimensional Data Communications

Two-Dimensional Data CommunicationsAn effective data interconnect fabric must support low latency and deterministic data transfers occurring simultaneously among multiple processing elements. It must also be flexible and scalable to allow for the addition of new elements or the removal of unwanted elements without affecting the rest of the design. Finally, it should be compatible with existing processors and be as easy to use as accessing memory.Memory-Like InterfaceUsing conventional bus cycles to transfer data between processors dispenses with exotic and hard-to-implement communications peripherals and protocols in favor of a simple memory-like interface. As shown in Figure 4, 2D-fabric from CrossBow appears to processors as a memory-mapped peripheral on an IBM CoreConnect™ bus. PowerPC and MicroBlaze processors can issue conventional read and/or write bus cycles to their local 2D-fabric peripherals to communicate with other processors on the chip (Figures 5 and 6). The payload for each transfer is derived from the data bus. The destination location and the initial direction of travel are derived from the address bus. The transfers are totally transparent to the sending and receiving processors, launching transfers with write cycles and terminating transfers with read cycles.Routing of data from source to destination, as well as arbitration with other data traffic, is performed autonomously by the interconnected 2D-fabric peripherals.A 2D Array of Data Transport LinksEfficient 3G designs will feature global communication fabrics using single sets of lines to transfer all kinds of data, including payloads, control words, and configuration data. Duplication of data transfer lines reduces overall system efficiency.As shown in Figure 7, 2D-fabric peripherals of adjacent processors are interconnected with a single mesh of horizontal and vertical data transport links. Individual bus cycles are autonomously converted to small packets that travel between source processors and destination processors through chains of 2D-fabric peripherals of the intermediate processors along the way. Short point-to-point links reduce power consumption.Small packets with single word payloads reduce data transfer latencies, enabling data and control packets to share common transfer lines. The same lines can also be used for system initialization and configuration.ScalabilityScalability is an important requirement for the design effort and product field upgrades. Constantly changing standards may require adding or removing processors late in the design cycle or even after field deployment.In the past, adding or removing processors has always been difficult when using centralized DMAs for movement of data. In any centralized I/O structure, removing or adding new components is likely to affect other system components. Two-dimensional I/O structures are much less sensitive to design changes. Adding another processor to a chip is as simple as wrapping it with a 2D-fabric peripheral and connecting the respective data transport links to the existing fabric. This can be easily done without affecting any hardware or software already in place.